The present invention relates to a clock synchronizing circuit for generating a clock which is synchronized with an input signal.
In a conventional clock synchronizing circuit which deals with a modulation signal yielded according to quadrature modulation, clock phase is obtained by using signal which is sampled in such away that in-phase component and orthogonal component of demodulation base band signal are sampled by a sampler respectively. FIG. 1 shows such the conventional clock synchronizing circuit. In FIG. 1, a sampler 301 implements sampling of in-phase input signal xe2x80x98SINIxe2x80x99 using sampling clock xe2x80x98SMPCLKxe2x80x99, before outputting as in-phase input sampling signal xe2x80x98SISAMPxe2x80x99. Further, sampler 302 implements sampling of orthogonal input signal xe2x80x98SINQxe2x80x99 using sampling clock xe2x80x98SMPCLKxe2x80x99, before outputting as orthogonal input sampling signal xe2x80x98SQSAMPxe2x80x99. Furthermore, angle detector 109 which inputs thereto these in-phase input sampling signal xe2x80x98SISAMPxe2x80x99 and orthogonal input sampling signal xe2x80x98SQSAMPxe2x80x99, to obtain xe2x80x9ctanxe2x88x921xe2x80x9d (SQSAMP/SISAMP), before finding phase of symbol clock to output as phase signal xe2x80x98SPxe2x80x99.
Moreover, a sequencer 303 which inputs thereto a sequence start signal xe2x80x98SSTxe2x80x99, before outputting an initial phase establishment signal xe2x80x98SSETPxe2x80x99. A sampling clock generation circuit 304 which inputs thereto a phase signal xe2x80x98SPxe2x80x99 and an initial phase establishment signal xe2x80x98SSETPxe2x80x99, before outputting a sampling clock xe2x80x98SMPCLKxe2x80x99 undergoing phase control such that the symbol clock is synchronized with both of the in-phase input signal xe2x80x98SINIxe2x80x99 and the orthogonal input signal xe2x80x98SINQxe2x80x99 with the initial phase establishment signal xe2x80x98SSETPxe2x80x99 as input. According to the operation as above, it is capable of implementing initial phase synchronization of the clock.
However, there is the problem that although such the conventional clock synchronizing circuit is capable of being applied in the case of dealing with modulation signal according to quadrature modulation, such the conventional clock synchronizing circuit is incapable of being applied in the case of use of modulation system of, for instance, xe2x80x98FSKxe2x80x99 and so forth except therefor.
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problem, to provide a clock synchronizing circuit which enables initial phase synchronization of the clock to be realized even though in the case of modulation system except for quadrature modulation in such a way that it uses cosine/sine output circuit for finding cosine component and sine component of initial phase of the symbol clock with simple constitution.
According to a first aspect of the present invention, in order to achieve the above-mentioned object, there is provided a clock synchronizing circuit which comprises a sampler inputting thereto an input signal and a sampling clock, before outputting sampling signal by sampling the input signal with the condition of xe2x80x98Nxe2x80x99 times of symbol rate, a sequencer for inputting thereto a symbol clock, a sequence start signal, and the sampling clock, before outputting a sign switching signal, a cosine component integration signal, a sine component integration signal, and an initial phase establishment signal, a cosine/sine output circuit inputting thereto an integration clock, the sampling signal, the sign switching signal, the cosine component integration signal, and the sine component integration, before outputting a cosine signal corresponding to cosine component of an initial phase of the symbol clock and a sine signal corresponding to a sine component of the initial phase of the symbol clock, an angle detector inputting thereto the cosine signal and the sine signal, before obtaining initial phase of the symbol clock, thus outputting it as an initial phase signal, a sampling clock generation circuit inputting thereto the initial phase signal and the initial phase establishment signal, before outputting both of the sampling clock which has fixed phase before initial phase establishment, and which is subjected to phase control in such a way that the symbol clock is synchronized with the input signal at the time of initial phase establishment, and the integration clock, and a frequency divider for dividing the sampling clock into symbol clock with 1/N times frequency in order to input it to the sequencer.
According to a second aspect of the present invention, there is provided a clock synchronizing circuit which comprises a sampler inputting thereto an input signal and a sampling clock, before outputting sampling signal by sampling the input signal with the condition of xe2x80x98Nxe2x80x99 times of symbol rate, a sequencer for inputting thereto a symbol clock, a sequence start signal, and the sampling clock, before outputting a sign switching signal, a cosine/sine selection signal, and an initial phase establishment signal, a cosine/sine output circuit inputting thereto an integration clock, the sampling signal, the sign switching signal, and the cosine/sine selection signal, before outputting a cosine signal corresponding to cosine component of an initial phase of the symbol clock and a sine signal corresponding to a sine component of the initial phase of the symbol clock, an angle detector inputting thereto the cosine signal and the sine signal, before obtaining initial phase of the symbol clock, thus outputting it as an initial phase signal, a sampling clock generation circuit inputting thereto the initial phase signal and the initial phase establishment signal, before outputting both of the sampling clock which has fixed phase before initial phase establishment, and which is subjected to phase control in such a way that the symbol clock is synchronized with the input signal at the time of initial phase establishment, and the integration clock, and a frequency divider for dividing the sampling clock into symbol clock with 1/N times frequency in order to input it to the sequencer.
According to a third aspect of the present invention, in the first aspect, there is provided a clock synchronizing circuit, wherein the cosine/sine output circuit comprises a sign switching circuit inputting thereto the sampling signal and the sign switching signal, before outputting either the sampling signal or a signal obtained by inverting the sampling signal as switching sampling signal in answer to the sign switching signal, a first integrator inputting thereto the switching sampling signal, the cosine component integration signal, and the integration clock, before outputting signal obtained by integrating the switching sample signal as an integration cosine signal only during period which becomes effective due to the cosine component integration signal, a second integrator inputting thereto the switching sampling signal, the sine component integration signal, and the integration clock, before outputting signal obtained by integrating the switching sampling signal as an integration sine signal only during period which becomes effective due to the sine component integration signal, a first averaging circuit inputting thereto the integration cosine signal, before outputting the cosine signal which is obtained while averaging according to the number of times of integration, and a second averaging circuit inputting thereto the integration sine signal, before outputting the sine signal which is obtained while averaging according to the number of times of integration.
According to a fourth aspect of the present invention, in the second aspect, there is provided a clock synchronizing circuit, wherein the cosine/sine output circuit comprises a sign switching circuit inputting thereto the sampling signal and the sign switching signal, before outputting either the sampling signal or a signal obtained by inverting the sampling signal as switching sampling signal in answer to the sign switching signal, a cosine/sine selection circuit inputting thereto the switching sampling signal, and the cosine/sine selection signal, before outputting the switching sampling signal as a cosine component signal when being selected as a cosine component, while outputting the switching sampling signal as a sine component signal when being selected as a sine component, a first integrator inputting thereto the cosine component signal and the integration clock, before outputting an integration cosine signal obtained by integrating the cosine component signal, a second integrator inputting thereto the sine component signal, and the integration clock, before outputting an integration sine signal obtained by integrating the sine component signal, a first averaging circuit inputting thereto the integration cosine signal, before outputting the cosine signal which is obtained after averaging according to the number of times of integration, and a second averaging circuit inputting thereto the integration sine signal, before outputting the sine signal which is obtained after averaging according to number of integration.
According to a fifth aspect of the present invention, there is provided a clock synchronizing circuit, wherein the input signal has an interval in which change that the input signal changes from the maximum value to the minimum value within half cycle of the symbol clock and further returning to the maximum value within the latter half cycle is repeated periodically, clock with speed of xc2xd times of the symbol clock is employed for the sign switching signal, the symbol clock is employed for the cosine component integration signal, signal obtained by inverting the cosine component integration signal is employed for the sine component integration signal, and clock with speed of 2 times of the symbol clock is employed for the integration clock.
According to a sixth aspect of the present invention, there is provided a clock synchronizing circuit, wherein the input signal has an interval in which change that the input signal changes from the maximum value to the minimum value within half cycle of the symbol clock and further returning to the maximum value within the latter half cycle is repeated periodically, clock with speed of xc2xd times of the symbol clock is employed for the sign switching signal, the symbol clock is employed for the cosine/sine selection signal, and clock with speed of 2 times of the symbol clock is employed for the integration clock.
As described above, according to the aspects of the present invention, the cosine/sine output circuit inputs thereto the integration clock, the sampling signal, the sign switching signal, the cosine component integration signal, and the sine component integration signal, before obtaining cosine signal corresponding to cosine component of initial phase of the symbol clock and sine signal corresponding to sine component of the initial phase of the symbol clock. The angle detector inputs thereto the cosine signal and the sine signal, before obtaining the initial phase of the symbol clock. It is capable of realizing surely initial phase synchronization of the clock even though the modulation system is the modulation system except for quadrature modulation.
The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the same is read in connection with the accompanying drawings. It should be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention.